1. Field of the Invention
The invention relates to a method of fabricating a flash memory. More particularly, the present invention relates to a method of fabricating a self-aligned split gate of a flash memory.
2. Description of the Related Art
At present, nonvolatile memory is widely used in the whole range of electrical devices. In particular, programmable nonvolatile memory having a flash memory structure such as the erasable programmable read-only memory (EPROM) and the electrically erased programmable read-only memory (EEPROM) has attracted immense interest.
In general, a flash memory comprises two gates, a floating gate for charge storage and a control gate for data accessing. The floating gate is in a floating state without being connected to any electrical circuit and is located between the control gate and a substrate while the control gate is connected to a word line.
An over-erase phenomenon easily occurs when erasing the conventional flash memory, so that verification circuits must necessarily be formed in the periphery region of the substrate on verify the memory cells and further to avoid the over-erase problem. However, the processes for fabricating a flash memory, including the additional steps for the verification circuits is complicated and the cost of the fabricating process is increased. In order to overcome the problems of the conventional flash, a split-gate flash memory is developed.
FIG. 1A-1D are schematic, cross-sectional views illustrating a method of fabricating a split gate for a flash memory cell according to the prior art method.
Referring to the FIG. 1A, a tunneling oxide layer 102 is formed on a substrate 100. Therefore, a polysilicon layer is formed and patterned to form a floating gate layer 104. Referring to FIG. 1B, a dielectric layer 106 and another conducting layer 108 are formed, and then the conducting layer 108 is patterned by a photolithography process and an etching process to form a control gate layer 108a of the split-gate of the flash memory cell, as shown in FIG. 1C. Referring to FIG. 1D, with the control gate layer 108a and the floating gate layer 104 serving as an implant mask, an ion implantion is performed to implant dopant in the substrate 100, so that a source 110 and a drain 112 are formed. Thereafter, a part of the dielectric layer 106 and a part of the tunneling oxide layer 102 are removed by a wet etching process, and the dielectric layer 106a and the tunneling oxide layer 102a under the control gate layer 108a are left. Consequently, the split-gate of the flash memory cell is completed.
In the about-mentioned process of fabricating the split-gate of flash memory cell, if misalignment occurs during the process of patterning the polysilicon layer 108 for forming the control gate layer 108a, the position of the control gate layer 108a is changed.
Since the channel length 120 of the control gate 108a profoundly affects the performance of the flash memory cell, it is important to controlling the channel length 120 of the control gate 108a in the process. Furthermore, changes in the channel length 120 of the control gate 108a affects the erase and the program operations of the split-gate of the flash memory.
Positive charges are injected into the floating gate 104 while erasing the split-gate of the flash memory, so that negative charges correspondingly rise in the floating channel region 130 of the substrate 100. The rising negative charges are equivalent to a virtual extended structure of the source 110. If the channel length 120 of the control gate 108a is shortened because of misalignment, the over-erase phenomenon easily occurs and the performance margin is reduced. Furthermore, the shortened channel length 120 causes the short channel effect and leads a part of the sub-threshold current into the floating gate 104, therefore affecting the capacitance of the split-gate of the flash memory.
On the other hand, the floating gate channel region 130 is in an off state after a program operation; the punch-through margin of the split-gate of the flash memory is limited by the distance between the source 110 and the drain 112 and is limited by the junction depth of the source 110 and the drain 112. Consequently, shortening the channel length 120 of the control gate by misalignment leads to a reduction in the distance between the source 110 and the drain 112, so that punch-through occurs in the whole region between the source 110 and the drain 112.